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general description the max4820/max4821 8-channel relay drivers offer built-in kickback protection and drive +3.3v/+5v non- latching or dual-coil-latching relays. these devices are especially useful when driving +3v relays. each inde- pendent open-drain output features a 2 on-resistance and is guaranteed to sink 70ma (min) of load current. both devices consume less than 50? (max) quiescent current and have 1? output off-leakage current. the max4820 features an spi-/qspi-/microwire- compatible serial interface. input data is shifted into an 8- bit shift register and latched to the outputs when cs transitions from low to high. each data bit in the shift reg- ister corresponds to a specific output, allowing indepen- dent control of all outputs. the max4821 features a 4-bit (a0, a1, a2, lvl) paral- lel-input interface. the first three bits (a0, a1, a2) deter- mine the output address, and the fourth bit (lvl) determines whether the selected output is switched on or off. data is latched to the outputs when cs transi- tions from low to high. both devices feature separate set and reset functions that allow the user to turn on or turn off all outputs simul- taneously with a single control line. built-in hysteresis (schmidt trigger) on all digital inputs allows this device to be used with slow rising and falling signals, such as those from optocouplers or rc power-up initialization circuits. the max4820/max4821 are available in 20-pin tssop and space-saving 20-pin thin qfn packages. applications central office ate dsl, adsl line cards industrial equipment e1/t1 redundancy features 8 independent output channels built-in inductive kickback protection drive +3v and +5v relays guaranteed 70ma (min) coil drive current set function to turn on all outputs simultaneously reset function to turn off all outputs simultaneously spi-/qspi-/microwire-compatible serial interface (max4820) serial digital output for daisy chaining (max4820) parallel interface (max4821) low 50 a (max) quiescent supply current space-saving 20-pin thin qfn package max4820/max4821 +3.3v/+5v, 8-channel, cascadable relay drivers with serial/parallel interface ________________________________________________________________ maxim integrated products 1 top view *connect ep to gnd. *ep 20 19 18 17 set v cc out1 out2 16 pgnd 13 12 11 14 15 out5 com out4 out3 out6 4 3 2 1 sclk din cs reset 5 dout 6 7 8 9 n.c. gnd out8 out7 10 pgnd max4820 thin qfn pin configurations ordering information 19-2751; rev 1; 4/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. * ep = exposed pad. pin configurations continued at end of data sheet. typical application circuits and functional diagrams appear at end of data sheet. spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. part temp range pin-package max4820 etp -40? to +85? 20 thin qfn-ep* max4820eup -40? to +85? 20 tssop max4821 etp -40? to +85? 20 thin qfn-ep* max4821eup -40? to +85? 20 tssop
max4820/max4821 +3.3v/+5v, 8-channel, cascadable relay drivers with serial/parallel interface 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = +3v to +5.5v, v com = v cc , t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages referenced to gnd.) v cc , com..............................................................-0.3v to +6.0v out_........................................................-0.3v to (v com + 0.3v) cs , sclk, din, set , reset , a0, a1, a2, lvl......-0.3v to +6.0v dout..........................................................-0.3v to (v cc + 0.3v) continuous out_ current (all outputs turned on) ............150ma continuous out_ current (single output turned on) ........300ma continuous power dissipation (t a = +70?) 20-lead thin qfn (derate 16.9mw/? above +70?) .................................1350mw ja (note 1)............................................................59.3?/w 20-pin tssop (derate 21.7mw/? above +70?) .................................1739mw ja (note 1)...............................................................46?/w operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? soldering temperature (10s) ...........................................+300? parameter symbol conditions min typ max units operating voltage v cc 2.3 5.5 v v cc = 3.6v 15 50 quiescent current i q i out _ = 0, logic inputs = 0v or v cc v cc = 5.5v 20 70 ? thermal shutdown 160 ? power-on reset 0.8 1.5 2.2 v power-on reset hysteresis 140 mv digital inputs (sclk, din, cs , lvl, a0, a1, a2, reset , set ) v cc = 3.3v 2.0 input logic-high voltage v ih v cc = 5v 2.4 v v cc = 3.3v 0.6 input logic-low voltage v il v cc = 5v 0.8 v input logic hysteresis v hyst 150 mv input leakage currents i leak input voltages = 0v or 5.5v -1.0 0.01 +1.0 a c in input capacitance c in 5pf digital output (dout) dout low voltage v ol i sink = 6ma 0.4 v dout high voltage v oh i source = 0.5ma v cc - 0.5 v relay output drivers (out1?ut8) v cc = 2.7v 70 out_ drive current v cc = 4.5v 70 ma out_ on-resistance r on v cc = 2.7v 2 6 out_ voltage v out _v cc = 3.0v, i out _ = 70ma 0.4 v i out off-leakage current i leak v out _ = v cc , all outputs off -1 +1 ? kickback diode forward voltage v forw i out _ = 150ma (note 3) 1.5 v note 1: package thermal resistances were obtained using the method described in jedec specifications. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial .
max4820/max4821 3.3v/+5v, 8-channel, cascadable relay drivers with serial/parallel interface _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units spi timing (max4820) turn-on time (out_) t on from rising edge of cs , r l = 50 , c l = 50pf 1.0 ? turn-off time (out_) t off from rising edge of cs , r l = 50 , c l = 50pf 1.0 ? sclk frequency f sclk 0 2.1 mhz cycle time t ch + t cl 480 ns cs fall to sclk rise setup t css 240 ns cs rise to sclk hold t csh 240 ns sclk high time t ch 190 ns sclk low time t cl 190 ns data setup time t ds 100 ns data hold time t dh 0ns sclk fall to dout valid t do 50% of sclk to 10% of dout, c l = 50pf 85 120 ns rise time (din, sclk, cs , set , reset ) t scr 20% of v cc to 70% of v cc , c l = 50pf 2 s fall time (din, sclk, cs , reset , set ) t scf 20% of v cc to 70% of v cc , c l = 50pf 2 s reset min pulse width t rw 70 ns set min pulse width t sw 70 ns parallel timing (max4821) turn-on time t on from rising edge of cs , r l = 50 , c l = 50pf 1s turn-off time t off from rising edge of cs , r l = 50 , c l = 50pf 1s lvl setup time t ls 100 ns lvl hold time t lh 0ns address to cs setup time t ah 100 ns address to cs hold time t as 0ns rise time (a2, a1, a0, lvl) t scr 20% of v cc to 70% of v cc , c l = 50pf 2 s fall time (a2, a1, a0, lvl) t scf 20% of v cc to 70% of v cc , c l = 50pf 2 s reset pulse width t rw 70 ns set pulse width t sw 70 ns electrical characteristics (continued) (v cc = +3v to +5.5v, v com = v cc , t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 2) note 2: specifications at -40? are guaranteed by design and not production tested. note 3: after relay turn-off, inductive kickback may momentarily cause the voltage at out_ to exceed v com . this is considered part of normal operation and will not damage the device.
max4820/max4821 +3.3v/+5v, 8-channel, cascadable relay drivers with serial/parallel interface 4 _______________________________________________________________________________________ typical operating characteristics (v com = v cc , t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) supply current vs. supply voltage max4820 toc01 supply voltage (v) supply current ( a) 5.1 4.7 4.3 3.9 3.5 3.1 2.7 5 10 15 20 25 0 2.3 5.5 all logic inputs = 0 supply current vs. temperature max4820 toc02 temperature ( c) supply current ( a) 60 35 10 -15 5 10 15 20 25 0 -40 85 v cc = 5v v cc = 5.5v v cc = 2.3v v cc = 3.3v supply current vs. input logic voltage max4820 toc03 input logic voltage (v) supply current ( a) 4 3 2 1 100 200 300 400 500 600 700 800 900 1000 0 05 v cc = 3.3v v cc = 5v all logic inputs connected on-resistance vs. supply voltage max4820 toc04 supply voltage (v) r on ( ) 5.1 4.7 4.3 3.9 3.5 3.1 2.7 0.5 1.0 1.5 2.0 2.5 3.0 0 2.3 5.5 i out_sink = 70ma on-resistance vs. temperature max4820 toc05 temperature ( c) r on ( ) 60 35 10 -15 0.5 1.0 1.5 2.0 2.5 3.0 0 -40 85 v cc = 3.3v v cc = 2.3v v cc = 5.5v v cc = 5v i out_sink = 70ma power-on reset voltage vs. temperature max4820 toc06 temperature ( c) power-on reset voltage (v) 60 35 -15 10 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0 -40 85 output off-leakage current vs. supply voltage max4820 toc07 supply voltage (v) output off-leakage (na) 5.1 4.7 3.9 4.3 3.1 3.5 2.7 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 2.3 5.5 output off-leakage current vs. temperature max4820 toc08 temperature ( c) output off-leakage (na) 60 35 -15 10 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0 -40 85 v cc = 5.5v v cc = 5v v cc = 2.3v v cc = 3.3v out_ turn-on/turn-off delay times vs. supply voltage max4820 toc09 supply voltage (v) t on /t off delay time (ns) 5.1 4.7 4.3 3.9 3.5 3.1 2.7 30 40 50 60 70 80 20 2.3 5.5 r l = 50 c l = 50pf t on t off
max4820/max4821 3.3v/+5v, 8-channel, cascadable relay drivers with serial/parallel interface _______________________________________________________________________________________ 5 input logic threshold vs. supply voltage max4820 toc10 supply voltage (v) input logic threshold (v) 5.1 4.7 2.7 3.1 3.5 3.9 4.3 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 0.50 2.3 5.5 pin max4820 max4821 thin qfn tssop thin qfn tssop name function 1313 reset reset input. drive reset low to clear all latches and registers (all outputs are turned off). reset overrides all other inputs. if reset and set are pulled low at the same time, then reset takes precedence. 2424 cs chip-select input. max4820: drive cs low to select the device. when cs is low, data at din is clocked into the 8-bit shift register on sclk? rising edge. drive cs from low to high to latch the data to the registers and activate the appropriate relays. max4821: drive cs low to select the device and set level on lvl. drive cs from low to high to latch the address and level data to the output. 3 5 din serial-data input 4 6 sclk serial-clock input 5 7 dout serial-data output. dout is the output of the 8-bit shift register. this output can be used to daisy chain multiple max4820s. the data at dout appears synchronous to sclk? falling edge. 6 8 n.c. no connection 7 9 7 9 gnd ground 8 10 8 10 out8 open-drain output 8. connect out8 to the low side of a relay coil. this output is pulled to pgnd when activated, but otherwise is high impedance. 9 11 9 11 out7 open-drain output 7. connect out7 to the low side of a relay coil. this output is pulled to pgnd when activated, but otherwise is high impedance. 10, 16 12, 18 10, 16 12, 18 pgnd power ground. pgnd is a return for the output sinks. connect pgnd pins together and to gnd. 11 13 11 13 out6 open-drain output 6. connect out6 to the low side of a relay coil. this output is pulled to pgnd when activated, but otherwise is high impedance. typical operating characteristics (continued) (v com = v cc , t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) back emf clamping with standard 3v relay max4820 toc11 200 s/div v cs 5v/div 0 0 out_ 1v/div out_ turns off v cc = 3.3v pin description
max4820/max4821 +3.3v/+5v, 8-channel, cascadable relay drivers with serial/parallel interface 6 _______________________________________________________________________________________ detailed description the max4820/max4821 8-channel relay drivers offer built-in kickback protection and drive +3.3v/+5v non- latching or dual-coil-latching relays. these devices are especially useful when driving +3v relays. each inde- pendent open-drain output features a 2 on-resistance and is guaranteed to sink 70ma (min) load current. both devices consume less than 50? (max) quiescent cur- rent and feature 1? (min) output off-leakage current. the max4820 features an spi/qspi/microwire-com- patible serial interface. input data is shifted into an 8-bit shift register and latched to the outputs when cs transi- tions from low to high. each data bit in the shift register corresponds to a specific output, allowing independent control of all outputs. the max4821 features a 4-bit (a0, a1, a2, lvl) parallel input interface. the three bits (a0, a1, a2) determine the output address, and lvl determines whether the selected output is switched on or off. data is latched to the outputs when cs transitions from low to high. both devices feature separate set and reset functions that allow the user to turn on or turn off all outputs simultaneously with a single control line. built-in hys- teresis (schmidt trigger) on all digital inputs allows this device to be used with slow rising and falling signals, such as those from optocouplers or rc power-up ini- tialization circuits. the max4820/max4821 are avail- able in 20-pin tssop and space-saving 20-pin thin qfn packages. pin max4820 max4821 thin qfn tssop thin qfn tssop name function 12 14 12 14 out5 open-drain output 5. connect out5 to the low side of a relay coil. this output is pulled to pgnd when activated, but otherwise is high impedance. 13 15 13 15 com common free-wheeling diodes. connect com to v cc . com can also be connected to a separate supply that is higher than v cc . in that case, bypass v cc to gnd with a 0.1? capacitor. 14 16 14 16 out4 open-drain output 4. connect out4 to the low side of a relay coil. this output is pulled to pgnd when activated, but otherwise is high impedance. 15 17 15 17 out3 open-drain output 3. connect out3 to the low side of a relay coil. this output is pulled to pgnd when activated, but otherwise is high impedance. 17 19 17 19 out2 open-drain output 2. connect out2 to the low side of a relay coil. this output is pulled to pgnd when activated, but otherwise is high impedance. 18 20 18 20 out1 open-drain output 1. connect out1 to the low side of a relay coil. this output is pulled to pgnd when activated, but otherwise is high impedance. 19 1 19 1 v cc input supply voltage. bypass v cc to gnd with a 0.1? capacitor. 20 2 20 2 set set input. drive set low to set all latches and registers high (all outputs are turned on). set overrides all parallel and serial control inputs. reset overrides set under all conditions. 3 5 lvl level input. lvl determines whether the selected address is switched on or off. a logic high on lvl switches on the addressed output. a logic low on lvl switches off the addressed output. 4 6 a0 digital address ??input. (see table 2 for address mapping.) 5 7 a1 digital address ??input. (see table 2 for address mapping.) 6 8 a2 digital address ??input. (see table 2 for address mapping.) ep exposed pad (thin qfn only). connect exposed pad to gnd. pin description (continued)
digital interface serial interface (max4820) the serial interface consists of an 8-bit shift register and parallel latch controlled by sclk and cs . the input to the shift register is an 8-bit word. each data bit controls one of the eight outputs, with the most signifi- cant bit (d7) corresponding to out8 and the least sig- nificant bit (d0) corresponding to out1 (see table 1). when cs is low (device is selected), data at din is clocked into the shift register synchronously with sclk? rising edge. driving cs from low to high latches the data in the shift register to the parallel latch. dout is the output of the shift register. data appears on dout synchronously with sclk? falling edge and is identical to the data at din delayed by eight clock cycles. when shifting the input data, d7 is the first bit in and out of the shift register. while cs is low, the switches always remain in their pre- vious state. drive cs high after 8 bits of data have been shifted in to update the output state and inhibit further data from entering the shift register. when cs is high, transitions at din and sclk have no effect on the out- put, and the first input bit (d7) is present at dout. if the number of data bits entered while cs is low is greater or less than 8, the shift register contains only the last 8 data bits, regardless of when they were entered. the 3-wire serial interface is compatible with spi, qspi, and microwire standards. the latch that drives the analog switch is updated on the rising edge of cs , regardless of sclk? state. parallel interface (max4821) the parallel interface consists of three address bits (a0, a1, a2) and one level selector bit (lvl). the address bits determine which output is updated, and the level bit determines whether the addressed output is switched on (lvl = high) or off (lvl = low). when cs is high, the address and level bits have no effect on the state of the outputs. driving cs from low to high latches the address and level data to the parallel register and updates the state of the outputs. address data entered after cs is pulled low is not reflected in the state of the outputs following the next low-to-high transition on cs (figure 2). max4820/max4821 3.3v/+5v, 8-channel, cascadable relay drivers with serial/parallel interface _______________________________________________________________________________________ 7 table 1. serial input address map (max4820 only) din d0 d1 d2 d3 d4 d5 d6 d7 out_ out1 out2 out3 out4 out5 out6 out7 out8 sclk din dout t css t cl t ch t csw t csh t do t on , t off t cso t ds t dh d7 d6 d1 d0 cs out_ figure 1. 3-wire serial-interface timing diagram (max4820 only)
max4820/max4821 set / reset functions the max4820/max4821 feature set and reset inputs that allow the user to simultaneously turn all outputs on or off using a single control line. drive set low to set all latch- es and registers to 1 and turn all outputs on. set over- rides all serial/parallel control inputs. drive reset low to clear all latches and registers and turn all outputs off. reset overrides all other inputs, including set . applications information daisy chaining the max4820 features a digital output, dout, that pro- vides a simple way to daisy chain multiple devices. this feature allows the user to drive large banks of relays using only a single serial interface. to daisy chain multi- ple devices, connect all cs pins together, and connect the dout of one device to the din of another device (see figure 3). during operation, a stream of serial data +3.3v/+5v, 8-channel, cascadable relay drivers with serial/parallel interface 8 _______________________________________________________________________________________ cs a_ lvl v out t as t ah t ls t lh t on , t off figure 2. parallel interface timing diagram (max4821 only) max4820 din din sclk sclk cs sclk dout out8 pgnd cs v cc v cc 0.1 f gnd out1 max4820 din sclk dout out8 pgnd cs v cc v cc 0.1 f gnd out1 max4820 din sclk dout out8 pgnd cs v cc v cc 0.1 f gnd out1 sclk figure 3. daisy-chain configuration table 2. parallel interface address map (max4821 only) a2 a1 a0 output low low low out1 low low high out2 low high low out3 low high high out4 high low low out5 high low high out6 high high low out7 high high high out8
is shifted through all the max4820s in series. when cs goes high, all outputs update simultaneously. the max4820 can also be used in a slave configuration that allows the user to address individual devices. connect all the din pins together, and use the cs input to address one device at a time. drive cs low to select a slave and input the data into the shift register. drive cs high to latch the data and turn on the appropriate outputs. typically, in this configuration only one slave is addressed at a time. max4820/max4821 3.3v/+5v, 8-channel, cascadable relay drivers with serial/parallel interface _______________________________________________________________________________________ 9 company phone website aromat corp. 310-524-9862 www.aromat.com cp clare corp. 978-524-6700 www.crouzet.com coto techonology 401-943-2686 www.cotorelay.com deustch relays, inc. 516-499-6000 www.deutschrelays.com fujitsu takamisawa 408-745-4900 www.fujitsufta.com hella kg hueck 734-414-0970 www.hella.com company phone website nec electronics, inc. 800-366-9782 www.nec-global.com omron electronics, inc. 847-843-7900 www.oeiweb.omron.com rockwell/allen- bradley 414-382-2000 www.ab.com siemens electromechanical component, inc. 770-371-3000 www.sec.siemens.com teledyne relays 213-777-0077 www.teledynerelays.com relay manufacturers typical application circuits max4820 reset set clk cs din dout out1 relay coil 1 relay coil 8 out8 com pgnd v cc v cc v cc 0.1 f gnd max4821 reset set a0 a1 cs lvl out1 relay coil 1 relay coil 8 out8 com pgnd v cc v cc v cc 0.1 f gnd a2
max4820/max4821 +3.3v/+5v, 8-channel, cascadable relay drivers with serial/parallel interface 10 ______________________________________________________________________________________ max4820 out1 out2 v cc reset parallel register 8-bit shift register set din dout sclk cs com out3 out4 out5 out6 out7 out8 pgnd gnd max4821 out1 out2 v cc reset parallel latch 4-to-8 decoder set lvl a0 cs com a2 a1 out3 out4 out5 out6 out7 out8 pgnd gnd functional diagrams
max4820/max4821 3.3v/+5v, 8-channel, cascadable relay drivers with serial/parallel interface ______________________________________________________________________________________ 11 chip information process: bicmos pin configurations (continued) 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 out1 out2 pgnd out3 cs reset set v cc out4 com out5 out6 a2 a1 a0 lvl 12 11 9 10 pgnd out7 out8 gnd max4821 tssop top view 20 19 18 17 set v cc out1 out2 16 pgnd 13 12 11 14 15 out5 com out4 out3 out6 4 3 2 1 a0 lvl cs reset 5 a1 6 7 8 9 a2 gnd out8 out7 10 pgnd max4821 thin qfn 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 out1 out2 pgnd out3 cs reset set v cc out4 com out5 out6 n.c. dout sclk din 12 11 9 10 pgnd out7 out8 gnd max4820 tssop *connect ep to gnd. *ep package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type package code document no. 20 tqfn-ep t2044-3 21-0139 20 tssop u20e-1 21-0108
max4820/max4821 +3.3v/+5v, 8-channel, cascadable relay drivers with serial/parallel interface maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 1/03 initial release 1 4/09 correct error in electrical characteristics table, style edits 1, 2, 3, 5, 11, 12, 13

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